# RADIX HEX

// send HS burst entry
# LP_STATES ACT
3 1

// send HSPrepare for 200 ns
# LP_STATES ACT 200
0 

// send HSZero for 200 ns
# HS_ZERO ACT 200

// send HSSync on active lanes
# HS_BYTES ACT
b8

// send Generic Write Packet
# HS_BYTES DEMUX
29 3 0 -1 1 2 3 -2

// send HS burst exit
# HS_BURST_EXIT

/////////////////////////////////////////////////////

// use HS_BURST_ENTRY for default timing
# HS_BURST_ENTRY

// send Generic Write Packet
# HS_BYTES DEMUX
29 -4 -1 1 2 3 4 -2

// send HS burst exit
# HS_BURST_EXIT

/////////////////////////////////////////////////////

// send one HS burst with 3 Generic Write Packets
# HS_PACKET
29 -4 -1 1 2 3 -2
29 -4 -1 1 2 3 4 -2
29 -4 -1 1 2 3 4 5 -2

/////////////////////////////////////////////////////

// Uncommment to test: requires lane count of 2 and HS bit rate of 200 Mbps

# IF 1
	# LP_STATES ACT
	3 1
	# LP_STATES ACT 200
	0 
	# HS_ZERO ACT 200
	# HS_BYTES ACT
	b8
	# HS_BYTES DEMUX
	29 5 0 25 1 2 3 4 5 13 dd

	// Build HSTrail manually
	// Total HS bits must match in each lane, requiring knowledge of packet demux position.
	// In two lane system, the packet will end at lane 1 meaning that lane 1 must have an
	// extra HSTrail byte.
	# HS_ONE 0 100
	# HS_ZERO 1 140

	# LP_STATES ACT
	3
# ENDIF